Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode

US7646177B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• David William Boerstler · Round Rock, US
• Eskinder Hailu · Austin, US
• Jieming Qi · Austin, US

Key dates

• Filing date: Dec 31, 2008
• Grant date: Jan 12, 2010
• Expiry date: Dec 31, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31727
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit may apply a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. The design structure may specify that control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.