Image processing and display scheme for rendering an image at high speed
US7646927B2 · kind B2 · utility
8Cited by
12References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Dec 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image processing apparatus includes: a block decompression unit that decompresses, block by block, a compressed code formed of a plurality of blocks into which image data is divided, where the compressed code is encoded block by block; and a rendering control unit that causes a code to be decompressed and rendered on a display unit, where the code corresponds to at least one of the blocks which one is renderable in the rendering region of the display unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.