Tuning DRAM I/O parameters on the fly
US7647467B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Apr 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
On the fly tuning of parameters used in an interface between a memory (e.g. high speed memory such as DRAM) and a processor requesting access to the memory. In an operational mode, a memory controller couples the processor to the memory. The memory controller can also inhibit the operational mode to initiate a training mode. In the training mode, the memory controller tunes one or more parameters (voltage references, timing skews, etc.) used in an upcoming operational mode. The access to the memory may be from an isochronous process running on a graphics processor. The memory controller determines whether the isochronous process may be inhibited before entering the training mode. If memory buffers for the isochronous process are such that the training mode will not impact the isochronous process, then the memory controller can enter the training mode to tune the interface parameters without negatively impacting the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.