Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor
US7647473B2 · kind B2 · utility
10Cited by
20References
16Claims
0Family size
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Key dates
| Filing date | Jan 24, 2002 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.