Method of identifying state nodes at the transistor level in a sequential digital circuit
US7647571B1 · kind B1 · utility
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2References
20Claims
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Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.