Method for manufacturing pixel structure
US7648865B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.