P-channel MOS transistor, semiconductor integrated circuit device and fabrication process thereof
US7649232B2 · kind B2 · utility
25Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode wherein each of the source and drain regions of p-type includes any of a metal film region and a metal compound film region as a compressive stress source accumulating therein a compressive stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.