Scan flip-flop with internal latency for scan input
US7649395B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2007 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jul 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.