Quality of phase lock and loss of lock detector
US7649421B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2007 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jun 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison. The window threshold may be a function of apriori knowledge of at least one loop variable, wherein the window threshold is set based on a predetermined loop variable. An alarm circuit may receive the fourth signal and provide an alarm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.