Electrostatic discharge protected circuits
US7649722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Mar 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.