Serial bus system
US7650450B2 · kind B2 · utility
5Cited by
25References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2005 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Mar 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial bus system for data communication between devices according to a master-slave protocol has a data bus connecting master and slave devices and a shared clock system arranged to provide a shared-clock signal to the master and slave devices. The master and slave devices are arranged to derive device-individual clock signals which are synchronized with data received on the data bus, from the shared-clock signal and a data-timing indication on the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.