Dynamic control of memory access speed
US7650481B2 · kind B2 · utility
15Cited by
9References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Dec 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is disclosed in which the access speed may be adjusted. The memory system may include memory and a memory controller. The memory controller may be configured to generate a plurality of control signals to access the memory, and adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.