Communication between processor core partitions with exclusive read or write to descriptor queues for shared memory space
US7650488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jun 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.