SPI-4.2 dynamic implementation without additional phase locked loops
US7650525B1 · kind B1 · utility
91Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jan 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for receiving clocked data signals such as SPI-4.2 data signals is described. In one embodiment, each data signal lane is deskewed with respect to the clock by oversampling the signal on that lane, and considering multiple versions of a data sequence at different temporal offsets to the clock for correct reception of a training sequence. One of the temporal offsets is subsequently selected to provide the received bit sequence for that lane. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.