Digital design component with scan clock generation

US7650549B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Charles M. Branch · Dallas, US
• Steven Craig Bartling · Plano, US
• Marc Royer · Garland, US
• Cory Dean Stewart · Sachse, US

Key dates

• Filing date: Jul 1, 2005
• Grant date: Jan 19, 2010
• Expiry date: Jan 26, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318552
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.