Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
US7651905B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2005 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/909
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.