Independently-double-gated combinational logic
US7652330B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2006 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Sep 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A family of logic circuits is constructed from double-gated four terminal transistors having independent gate control. First and second inputs to each logic element are independently coupled to the top and bottom gates of a transistor. The output voltage developed at either the source or drain represents an output logic state value according to the designed logic element. In a dynamic configuration the drain is precharged to an appropriate voltage. Complementary static CMOS configurations are also shown. Bottom Gates not driven by logic inputs or control signals may be biased to control the speed and power of the described logic circuits. Specific designs are given for AND, NAND, XOR, XNOR, OR and NOR combinational logic elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.