Integrated circuit with delay selecting input selection circuitry
US7652498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Dec 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.