Apparatus and method for exploiting reverse short channel effects in transistor devices
US7652519B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/21178
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of implementing a transistor circuit comprises coupling first and second transistors in parallel, wherein the first transistor has a channel length corresponding to a peak in the transistor's voltage threshold curve arising from reverse short channel effects, and the second transistor has a longer channel length and, therefore, a lower threshold voltage. Exploiting reverse short channel effects in this manner enables the implementation of “composite” transistor circuits that exhibit improved linearity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.