Front-end sampling technique for analog-to-digital converters
US7652611B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2008 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | May 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.