Memory module and register with minimized routing path
US7652949B2 · kind B2 · utility
1Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2006 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Sep 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.