Reconfigurable cache controller utilizing multiple ASIC SRAMS
US7653785B2 · kind B2 · utility
6Cited by
19References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2005 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Oct 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application specific integrated circuit (ASIC) is configured to perform image processing tasks on a printer or other multi-function device. The ASIC includes a processor, a dedicated cache memory, a cache controller and additional Static Random Access Memory (SRAM) normally employed in image processing tasks. This additional SRAM may be dynamically allocated as a cache memory when not otherwise occupied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.