Semiconductor device free of gate spacer stress and method of manufacturing the same
US7655525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.