Semiconductor devices and methods of forming the same
US7656008B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 2, 2008 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | May 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped regions. Spacers are on opposite sidewalls of gate electrode. A first surface metal silicide layer extends across a top surface of the first doped region adjacent to the spacer. A second surface metal silicide layer extends across a top surface of the second doped region adjacent to the spacer. At least one insulation layer extends across the semiconductor substrate including the first and second surface metal silicide layers. A first contact plug extends through the insulation layer and contacts the first surface metal silicide layer. A second contact plug extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well within the semiconductor substrate. Related methods of forming semiconductor devices are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.