Micro discharge (MD) plasma display panel (PDP) having perforated holes on both dielectric and electrode layers
US7656092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Sep 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2211/265
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A Plasma Display Panel (PDP) includes a dielectric layer having a plurality of dielectric-layer perforated holes arranged in a matrix; upper and lower electrode layers each having electrode-layer perforated holes connected to the dielectric-layer perforated holes and arranged on both surfaces of the dielectric layer, the upper and lower electrode layers being adapted to receive electrical signals. The upper electrode layer includes a plurality of upper electrodes extending in a first direction, each of the plurality of upper electrodes surrounding a group of the electrode-layer perforated holes arranged in the first direction and including transparent individual electrodes surrounding the electrode-layer perforated holes and linear connection portions adapted to electrically connect the individual electrodes. The lower electrode layer includes a plurality of lower electrodes extending in a second direction at an angle with respect to the first direction, each of the plurality of second electrodes surrounding a group of electrode-layer perforated holes arranged in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.