Incrementer based on carry chain compression
US7656190B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2009 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Jun 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive-OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.