Switched capacitor equalizer with offset voltage cancelling
US7656226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | May 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H19/004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment may be described as a switched capacitor analog equalizer circuit with offset voltage cancellation, where an embodiment comprises an amplifier in which a feedback path from its output port to one of its input ports is provided during a reset phase, and where the amplifier's input port connected to the feedback path is also connected to one terminal of an offset-correction capacitor and one terminal of a sampling capacitor. The other terminal of the offset-correction capacitor is connected to a switch and the other terminal of the sampling capacitor is connected to an input port to receive a signal. During the reset phase, the switch is open, and during a sampling phase, the switch is closed so that the offset-correction capacitor and the sampling capacitor are connected in parallel. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.