Semiconductor memory system including a plurality of semiconductor memory devices
US7656711B2 · kind B2 · utility
15Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2008 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.