Method and apparatus for reducing clock speed and power consumption
US7656907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2007 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Nov 10, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.