Stabilized digital timing recovery using low-complexity equalizer
US7656945B1 · kind B1 · utility
8Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A low-complexity digital linear equalizer whose operation and adaptation makes stabilized digital timing recovery practical. The technique is fundamental for the operation of communications receivers employing digital timing recovery, e.g., in a modem. A technique for automatically adjusting the parameters of a digital linear equalizer to compensate for low-pass impairments while maintaining a relatively constant timing characteristic is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.