Dual clock domain deskew circuit
US7656983B2 · kind B2 · utility
2Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.