Circuits and methods for recovering a clock signal
US7656984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2005 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | May 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.