Timestamp-based all digital phase locked loop for clock synchronization over packet networks
US7656985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Mar 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator and a timestamp counter. The all digital phase locked loop enables the CES receiver to synchronize a local clock at the receiver with a clock at a CES transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps. The phase detector is operable to compute an error signal indicative of differences between the timestamps and a local clock signal. The loop filter is operable to reduce jitter and noise in the error signal, and thereby produce a control signal. The digital oscillator is operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal. The timestamp counter operable to count pulses in the digital oscillator output signal, and output the local clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.