Method to detect NAND-flash parameters by hardware automatically
US7657696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Nov 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.