Secure memory caching structures for data, integrity and version values
US7657756B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Feb 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus that may be utilized to reduce latency associated with encryption based on externally stored security metadata are provided. When encrypted data is accessed for the first time, a cache line containing corresponding metadata used for decryption may be placed in an internal security metadata cache. If that data is accessed again, it may be retrieved without accessing external memory, thus reducing latency. Further, if adjacent data is accessed, the cached line may contain sufficient metadata to decrypt the adjacent data. As a result, a separate operation to access metadata for the adjacent data may be avoided, thus reducing latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.