Clock distribution chip for generating both zero-delay and non-zero-delay clock signals
US7657773B1 · kind B1 · utility
3Cited by
9References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Sep 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.