Low-complexity hybrid LDPC code encoder
US7657816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Jun 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G matrix multiplication method. In addition to the method an initial circuit is given for the G matrix multiplication encoder and the RU encoder. A circuit for the hybrid encoder is presented which achieves less power consumption and smaller area than an equivalent encoder based on the G matrix multiplication with a smaller critical path than previous encoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.