Dynamic minimum-memory interleaving
US7657818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Mar 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Minimum-memory-implementation is available with any depth and period in DSL interleaving/deinterleaving, always allowing the minimum amount of memory to be used in both transmitter and receiver without loss of performance or of basic triangular structure, even if the interleaver/deinterleaver parameters change dynamically. A novel cell-scheduling process ensures availability of the minimum amount of memory (or any other desired memory usage) to implement an image of the perfect triangle and works for any co-prime depth and interleaver period. Minimal memory use may be further characterized by a simple off-line method that determines an addressing order for each of the memory cells in a minimum-memory (or other) implementation of an interleaver/deinterleaver according to the invention. Time variation of interleaver depth in operation can be accommodated easily with absolute minimum memory requirement at all time instants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.