Patent · US Active

Automated electrostatic discharge structure placement and routing in an integrated circuit

US7657858B2 · kind B2 · utility

3Cited by

5References

20Claims

0Family size

Assignee

Agere Systems Inc. · US

Inventors

Youang Pin Chen · Allentown, US
Sireesha Tulluri Lakshmi Naga Venkata Srujana · Bengaluru, IN
Nirav Patel · Burlingame, US
Raghunatha Reddy · Bengaluru, IN
Sivaramakrishnan Subramanian · Savanuru, IN
Venkat Rao Vallapaneni · Bengaluru, IN

Key dates

Filing date	Nov 30, 2006
Grant date	Feb 2, 2010
Priority date	—
Expiry date	Mar 17, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.