System and method for phase-locked loop (PLL) for high-speed memory interface (HSMI)
US7659783B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Sep 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0998
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.