High speed signal transmission line having reduced thickness regions
US7659790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2006 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P3/003
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated systems and methods may include one or more features for high speed transmission line structures that may substantially reduce signal degradation due to effects, such as dielectric loss, parasitic capacitance, cross-talk, and/or reflections. For example, one such feature may include a dielectric layer having a reduced thickness within at least a part of a region that extends between two conductors fabricated on a PCB (printed circuit board). In some embodiments, the dielectric layer may include a solder mask layer that is partially or substantially absent in the region between two coplanar conductors. In another embodiment, a substrate layer made of a dielectric material may include a trench in the region between the two conductors. Another such feature, for example, may include a conductor having vias spaced less than a quarter wavelength apart to substantially reduce resonance effects on propagating high frequency signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.