Method, apparatus and program product to concurrently detect, repair, verify and isolate memory failures
US7661044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | May 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for repairing memory failure in a computer system in one aspect determines one or more test patterns and time duration for testing the new memory unit that replaced a failed memory unit. The test pattern is written to the new memory unit and read from the new memory unit. The read pattern is compared to the test pattern that was used to write. If the read test pattern and the written test pattern doe not match, a further repair action is taken. If they match, writing and reading of the test pattern repeats until the time duration for testing expires. The new memory unit may be configured as available for use when the write and read test completes successfully for the testing time duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.