Method and system for formal verification of partial good self test fencing structures
US7661050B2 · kind B2 · utility
14Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Mar 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318385
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.