System to reduce programmable range specifications for a given target accuracy in calibrated electronic circuits
US7661051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Mar 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.