High performance turbo and Viterbi channel decoding in digital signal processors
US7661059B2 · kind B2 · utility
1Cited by
15References
9Claims
0Family size
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Key dates
| Filing date | Aug 6, 2001 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Feb 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6569
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.