Method for fabricating reverse-staggered thin film transistor
US7662681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Dec 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0251
Abstract
Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.