Semiconductor die with reduced bump-to-pad ratio
US7663235B2 · kind B2 · utility
8Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2007 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a semiconductor die includes at least one pad ring situated on an active surface of the semiconductor die, where the at least one pad ring includes a number of pads. The semiconductor die further includes a number of bumps including at least one shared bump. The at least one shared bump is shared by at least two pads, thereby causing the number of bumps to be fewer than the number of pads. The at least two pads can be at least two ground pads, at least two power pads, or at least two reference voltage pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.