High voltage stress test circuit
US7663402B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 13, 2009 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jan 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.