Phase locked loop (PLL) method and architecture
US7663415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jan 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.