Clock systems and methods
US7663419B1 · kind B1 · utility
0Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2008 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and a multi-bit control signal. A clock skew circuit provides a delay to the clock signal based on the delay control signal provided by the control signal. Memory coupled to the control logic provides the multi-bit control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.